专利摘要:
Apparatus is provided for use in a digital video signal playback device of the type having a record medium in which plural channels of digital video signals are recorded in a like plurality of tracks. Plural transducers, such as playback heads, are associated with respective ones of the channels and reproduce the digital video signals from the plural tracks, each transducer normally reproducing a respective, predetermined channel of the digital video signals. A detector detects the particular channel with which the digital video signal reproduced by each transducer is associated. A signal interchanger is provided with plural channel outputs and is responsive to the detector for directing digital video signals which have been reproduced by transducers associated with channels which differ from the channels of the reproduced digital video signals to the proper channel outputs as determined by the detector. Thus, regardless of the particular transducer which reproduces the digital video signals from a track, that digital video signal nevertheless is supplied to its proper channel output.
公开号:SU1003774A3
申请号:SU802992248
申请日:1980-10-04
公开日:1983-03-07
发明作者:Ямаото Каити
申请人:Сони Корпорейшн (Фирма);
IPC主号:
专利说明:

The invention relates to magnetic recording, and in particular to devices for reproducing an analog color video signal from j magnetic tape.
A device is known for reproducing an analog color video signal from a magnetic tape, containing 10 first, second and third magnetic heads mounted on a rotating disk and connected to the inputs of the first, second and third playback amplifiers, respectively [1].
The known device has a relatively simple construction, but does not allow to provide sufficient simplicity of the process of reproducing an analog color video signal from a magnetic tape.
A device is also known for reproducing an analog color video signal from a magnetic tape, containing 25 first, second, and third magnetic heads mounted on a rotating disk and connected to the inputs of the first, second, and third playback amplifiers, '* connected to the inputs of the first, second, and third correctors temporary distortions, respectively, through the first, second and third playback processors, and the first, second and third decoding error correction elements connected to the inputs respectively continuously the first, second and third elements of timebase expansion, connected to the inputs of the interface, connected via a digital to analog converter, and an output processor to the output bus ana lots color video · r 2).
This device allows for the relative simplicity of the process of reproducing an analog color video signal from a magnetic tape. The disadvantage of such a device is a significant playback error.
The purpose of the invention is to reduce the error in reproducing analog color video signal from a magnetic tape.
This goal is achieved by the fact that in the device for reproducing .analog color video signal from · magnetic tape, containing the first, second and third magnetic heads mounted on the resultant disk connected to the inputs of the first, second and third playback amplifiers connected by the inputs of the first, second and the third time distortion corrector, respectively, through the first, second and third playback processors, and the first, second and third decoding error correction elements, n-10 to the inputs of the first, second, and third time expansion expansion elements, respectively, connected to the inputs of an interface connected via a digital-to-analog converter and an output processor with an analog video output bus, a data exchange unit consisting of an address counter, a generator is introduced control signals, signal recognition signal generators, control signal shapers, multiplexers, buffer storage elements and threshold elements, and each of the processors reproduces The reference consists of 4 bit synchronization units and a decoding unit connected in series and from inputs and outputs connected to them and connected · sequentially of an automatic phase adjustment unit and a synchronization signal extraction unit 30. The output of the first time distortion corrector is connected to the first threshold element and the second threshold element, the output of which is connected to the first input 35 of the first buffer storage element and connected through the third threshold element to the first input of the first multiplexer connected to the first output of the first output of the first 4Q of a signal trainer and a second multiplexer connected to the first input connected to the input of the first decoding element, error correction, the outputs of the first threshold of the first element is connected to the first data recognition signal generator, connected to the second input of the first buffer storage element and connected to the first output fm to the first input of the first driver of control signals, the output of the second time distortion corrector is connected to the fourth threshold element and to the fifth threshold element, the output of which is connected to the first 55th input of the second buffer storage element and is connected through the sixth threshold element to the first input of the third multiplexer, connected connected by the second input to the first 60 output of the second control signal generator and connected by the second input to the second output of the second control signal generator and connected to the input of the second decoding error correction element, the outputs of the fourth threshold element are connected to the second data recognition signal generator connected to the second input of the second 5 buffer memory element and the output connected to the first input of the second driver of control signals, the output of the third time corrector distortion is connected to the seventh threshold element and to the eighth threshold element, the output of which is connected to the first input of the third buffer storage element and connected through the ninth threshold element to the first input of the fifth multiplexer connected to the second input to the first output of the third driver, control signals and connected to the first the input of the sixth multiplexer connected by the second input to the second output of the third decoding error correction element, the outputs of the seventh threshold element connected to the third data recognition signal generator connected to the second input of the third buffer memory element and connected by the first output to the first input of the third control signal generator, the output of the first buffer memory element is connected through the tenth and eleventh threshold elements connected in series with the third inputs of the fourth and fifth multiplexers , the output of the second buffer storage element is connected via the twelfth and thirteenth connected in series th threshold elements to the third inputs of the first and sixth multiplexers, the output of the third buffer memory element is connected through fourteen and fifteenth threshold elements connected in series with the third inputs of the second and third multiplexers, the second and third outputs of the first data recognition signal generator 1 are connected to the first driver of control signals and to the second inputs of the second and third control signal conditioners, respectively, the second and third outputs of the second signal generator data directions are connected to the second control signal generator and to the second and third inputs of the first and third control signal generators, respectively, the second and third outputs of the third data recognition signal generator are connected to the third control signal generator and to the third inputs of the first and second control signal generators, and the control signal generator is connected to the inputs of the address counter, the output of which is connected to the third inputs of the first, second and third buffer storage elements, and with the inputs of the first, fourth and seventh threshold elements and the first, second and third generators 5 of data recognition signals.
The proposed device can significantly reduce the error in reproducing an analog color video signal from magnetic tape 10.
In FIG. 1 shows a structural diagram of one of the possible variants of the proposed device for reproducing an analog color video-15 signal from a magnetic tape; figure 2 block mutual exchange of data; in FIG. 3 - playback processor.
The device contains the first, second and third magnetic heads 1, -Q mounted on a rotating disk, and the first, second and third decoding error correction elements 2 connected to the inputs of the first, second and third time expansion expansion elements 3, respectively. The first, third, and third elements 3 of the expansion of the time base are connected to the inputs of the interface 4 connected via a digital-to-analog converter 5 and the output processor 6 with the output bus 7 of the analog color video signal. The first, second, and third magnetic heads 1 are connected to the inputs of the first, second, and third playback amplifiers 8, respectively, connected to the inputs of the first, second, and third time distortion corrector 9, respectively, through the first, second, and third playback processors 10. In this case, 40 each of the reproduction processors 10 consists of sequentially connected bit synchronization unit 11 and decoding unit 12 and of inputs and outputs 45 connected to them and sequentially connected phase automatic adjustment unit 13 and synchronization signal extraction unit 14.
The proposed device also contains a block 15 for the mutual exchange of data, which includes an address counter 16, a generator 17. control signals, the first, second and third generators 18-20 signal recognition data, the first, second and 33 third drivers 21-23 control signals, the first, second, third, fourth, fifth and sixth multiplexers 24-29, the first, second and third buffer storage elements 30-32 60 and the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh , twelfth, thirteenth, fourteen Attiyah and a fifteenth threshold elements £ 5
33-47. In this case, the output 48 of the first time distortion corrector 9 is connected to the first threshold element 33 and to the second threshold element 34, the output of which is connected to the first input of the first buffer storage element 30 and connected through the third threshold element 35 to the first input of the first multiplexer 24. The first multiplexer 24 connected by the second input to the first output of the first driver 21 of the control signals and connected to the first input of the second multiplexer 22 connected to the input 49 of the first de “coding element 2 correction about error The outputs of the first threshold element 33 are connected to the first data recognition signal generator 18, connected to the second input of the first buffer storage element 30 and connected to the first input of the first input of the first driver 21 of the control signals.
In the proposed device, the output of the second time distortion corrector 9 is connected to the fourth threshold element 36 and to the fifth threshold element 37, the output of which is connected to the first input of the second buffer storage element 31 and connected through the sixth threshold element 38 to the first input of the third multiplexer 26. Third multiplexer 26 connected to the first output of the second driver 22 of the control signals and connected to the first input of the fourth multiplexer 27 connected to the second input by the second input the second driver 22 of the control signals and connected to the input of the second decoding element 2 error correction. The outputs of the fourth threshold element 36 are connected to the second data recognition signal generator 19, connected to the second input of the second buffer memory element 31 and connected to the first input of the second driver 22 of the control signals.
The output 52 of the third time distortion corrector 9. Is connected to the seventh threshold element 39 and to the eighth threshold element 40, the output of which is connected to the first input of the third buffer memory e element 32 and connected through the ninth threshold element 41 to the first input of the fifth multiplexer 28. Fifth multiplexer 28 connected to the first output of the third driver 23 of the control signal and connected to the first input of the sixth multiplexer 29 connected to the second input of the third output of the third 23 control signals and connected to the input 53 of the third decoding element 2 error correction. The outputs of the seventh threshold element 39 are connected to the third 5 signal recognition signal generator 20, connected to the second input of the third buffer storage element 32 and connected by the first output to the first input of the third Yu of the driver 23 of the control signals.
In the proposed device, the output of the first buffer storage element 30 is connected via threshold elements 42 and 43 connected in series with the tenth and eleventh to 15 third inputs of the fourth and fifth multiplexers 27 and 28. The output of the second buffer memory element is connected through the twentieth and thirteenth consequently included threshold elements 44 and 45 to the third inputs of the first and sixth multiplexers 24 and 29. The output of the third buffer storage element is connected through fourteen connected in series the fifth and fifteenth threshold elements 46 and 47 with the third inputs of the second and third, multiplexers 25 and 26.
The second and third outputs of the first n-30 signal generator of the identification data 18 are connected to first formation Tieliu t 21 control signals and to second inputs of respectively the second and third generators 22 and 23 control 35 The signal catch. The second and third outputs of the second data recognition signal generator 19 are connected to the second driver 22 of the control signals and to the second and third inputs 40 of the first and third drivers 21 and 23, respectively. The second and third outputs of the third data identification signal generator 20 are connected to the third-45th driver 23 of the control signals and to the third inputs of the first and second drivers 21 and 22 of the control signals, respectively.
The generator 17 of control signals is connected to the inputs of the address counter 50 ka 16, the output of which is connected to the third inputs of the first, second and third buffer storage elements 30-32, and with the inputs of the first, fourth and seventh threshold elements 55, 33, 36 and 39 and the first, second and third generators 18-20 signal recognition data.
In the proposed device, during the reproduction process, the result of reproducing the digital signals of the first, second and third magnetic heads 1 after conversion is received from the outputs 48, 50 and 52 of the first, second and third time distortion correctors 9 to the data exchange unit 15. Block 15 of the mutual exchange of data processes the signals received on it in case of deviation from the normal playback mode. From the block 15 of the mutual exchange of data through the first, second and third decoding elements 2 error correction, the first, second and third elements 3 of the expansion of the time base and interface 4 to the “digital-to-analog converter 5. In the digital-to-analog converter 5, the digital signal is converted to an analog color video signal .
The invention can be used in video recorders designed for digital recording of television signals.
权利要求:
Claims (2)
[1]
1. The patent of Japan 53-3606, class 102 E 12, published. 08.02.78.
[2]
2. Japan patent 53-5125,
cl. 102 E 3, published. 02.24.78 (prototype).
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同族专利:
公开号 | 公开日
JPS5651174A|1981-05-08|
GB2064258A|1981-06-10|
NL8005526A|1981-04-07|
CA1165867A|1984-04-17|
FR2466925A1|1981-04-10|
AU540959B2|1984-12-13|
AT383923B|1987-09-10|
DE3036899A1|1981-04-23|
MX148064A|1983-03-09|
CH654133A5|1986-01-31|
SE450864B|1987-08-03|
BR8006396A|1981-04-14|
JPH056395B2|1993-01-26|
US4392162A|1983-07-05|
AU6268580A|1981-04-09|
DE3036899C2|1989-05-03|
FR2466925B1|1986-04-25|
ATA495980A|1987-01-15|
GB2064258B|1984-03-14|
SE8006920L|1981-04-05|
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法律状态:
优先权:
申请号 | 申请日 | 专利标题
JP54128338A|JPH056395B2|1979-10-04|1979-10-04|
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